Simulation and Modeling of Fractional-N sigma delta PLL for Quantisation Noise Optimisation
Simulation and Modeling of Fractional-N sigma delta PLL for Quantisation Noise Optimisation
Abstract—Wireless Communication has expanded and achieved great heights. It has increased demand for rate of data transmission using low noise clock. Fractional-N frequency synthesizer is used most commonly in today’s wireless technologies. This paper presents simulation and modeling of fractional-N frequency synthesizer and compares architectures that optimize quantization noise. Fractional-N frequency synthesizer is derived from integral-N frequency synthesizer using division control architectures such as Error Feedback Modulator (EFM), Multi-Stage Noise Shaping (MASH) and modified versions of MASH. Results show that fractional-N frequency synthesizer is capable of producing frequencies between 200MHz- 225MHz with a phase margin of 48°. Spurious noise is observed at -200dBc.
Keywords—fractional-N frequency synthesizer, CppSim, EFM, MASH I.
INTRODUCTION
Wireless applications like GSM, FM, EDGE etc. has limited number of bands and the local oscillators(LO) used in transceivers are expected to achieve these frequencies at low noise and high bandwidth. LO requires spanning a range of frequencies at an increment of fine resolution. It should be capable of hopping between channels in a short duration or at a great speed. This results in high bandwidth. LO are required to meet noise requirement such that it does not corrupt data or interfere on adjacent channels. LOs are achieved through Phase Locked Loops(PLLs). These PLLs mimic noise characteristic of crystal oscillator (reference oscillator). Integer-N frequency synthesizer is an application of PLL. It is capable of producing frequencies that are integer multiples of reference frequency. Therefore, the integer-N frequency synthesizer is limited by resolution [1]. The resolution is dependent on reference frequency and for smaller resolution, reference frequency should be reduced. Bandwidth of PLL is dependent on reference frequency. Reducing reference frequency results in reducing bandwidth. Fractional-N frequency synthesizer decouples resolution from bandwidth [2]. Due to the demand in high data rate and existence of more number of users have led to need for a design where interference and signal-to-noise ratio are key considerations. Phase noise and spurious noise affects the design considerations for frequency synthesizers. Minimizing phase noise and spurs of the frequency synthesizer while staying within power, size and cost constraints is a challenge for design engineers.