Power and Delay Analysis of Logic Circuits Using Reversible Gates
Soham Bhattacharya, Anindya Sen
Electronics and Communication Engineering Department, Heritage Institute of Technology, Kolkata, India
Abstract – This paper determines the propagation delay and on chip power consumed by each basic and universal gates and basic arithmetic functions designed using existing reversible gates through VHDL. Hence a designer can choose the best reversible gates to use for any logic circuit design. The paper does a look up table analysis of truth tables of the reversible gates to find the occurrence of the AND OR, NAND, NOR and basic arithmetic functions, useful to build complex combinational digital logic circuits.
Keywords — Reversible logic, Logic circuits, Power dissipation, Quantum cost, Timing analysis, On-chip power
I. INTRODUCTION
Dark silicon[1] problem has imposed several challenges in VLSI technology with power dissipation and design implementation. Consequently application of reversible logic has received attention in the recent years to reduce the power dissipation with low power VLSI design, and it has a vast impact in low power CMOS, quantum computation and nanotechnology.
According to Landauer[2,3], the amount of energy dissipated for every irreversible bit operation is at least KTln2 joules, where K=1.3806505*10-23m2kg-2K-1 (joule/Kelvin-1) is the Boltzmann’s constant and T is the absolute temperature at which operation is performed. A circuit is reversible if the input is recoverable from the output. Reversible computing supports both forward and backward movement process as one generates inputs from the outputs. In 1973, Bennett[4] showed that energy dissipation problem is avoided with circuits built using reversible logic gates.